1. Field of the Invention
The present invention relates to a method of producing a field effect transistor which is provided with a gate electrode, a source electrode and a drain electrode on a major surface of a semiconductor substrate and wherein an impurity contained in the source and drain electrodes is diffused by heat treatment into the semiconductor substrate to form a source area and a drain area. Particularly, the present invention is connected with a method of producing a side-wall insulating film for electrically insulating the source and drain electrodes from the gate electrode.
2. Description of the Background Art
FIG. 6 is a sectional view showing the structure of a MOS (Metal Oxide Semiconductor) field effect transistor which is a kind of a field effect transistor.
A thin gate film 2 is formed on the surface of a silicon substrate 1, and a gate electrode 3 is formed by a polycrystalline silicon on the gate oxide film 2. Further, a source area 4 and a drain area 5 are formed in the surface of the silicon substrate 1 on both sides of the gate electrode 3. The source and drain areas 4, 5 are formed by ion implantation into the silicon substrate 1 using the gate electrode 3 as a mask, followed by heat treatment. On the surface of the silicon substrate 1 there is formed a field oxide film 6 to separate semiconductor devices from each other. On the surface of the silicon substrate 1 and that of the gate electrode 3 there is formed an interlayer insulating film 7, on which are formed wiring layers 8a and 8b using aluminum. The source area 4 and the wiring layer 8a are connected together electrically by aluminum filled in a contact hole 9a formed in the interlayer insulating film 7, while the drain area 5 and the wiring layer 8b are electrically connected together by aluminum filled in a contact hole 9b formed in the interlayer insulating film 7.
Now, in a conventional MOS field effect transistor, the source region 4 and the drain region 5 are formed by directly implanting ions to the silicon substrate and thereafter by thermally diffusing the implanted ions. Consequently, crystal defects 4a and 5a are generated in the silicon substrate 1. The crystal defects degrade electric characteristics of the MOS field effect transistor. The crystal defects are generated in the region where the impurities stay. Namely, the crystal defects 4a and 5a are generated at lower portions of the source and drain regions 4 and 5.
FIG. 10A is a graph showing the relation between the current and the voltage in a device having no crystal defect at the pn junction. FIG. 10B is a graph showing the relation between the current and the voltage in a device having crystal defects at the pn junction. It can be seen that the pn junction breakdown voltage of the device having crystal defects at the pn junction (FIG. 10B) is considerably lower than that of the device having no crystal defect at the pn junction (FIG. 10A). Recently, moreover, there has been an increasing demand for miniaturization, speed-up and reduction or power consumption of MOS field effect transistors.
As a transistor free of such crystal defect caused by ion implantation near the surface of the silicon substrate and satisfying the demand for miniaturization, etc. of a MOS field effect transistor, there is a polysilicon source-drain transistor (hereinafter referred to as "PSD transistor").
FIG. 7 is a sectional view showing the structure of the PSD transistor. On the surface of a silicon substrate 11 is formed a thin gate oxide film 12a, on which is formed a gate electrode 13 by a polycrystalline silicon. The gate electrode 13 is T-shaped in section. A source area 14 and a drain area 15 are formed near the surface of the silicon substrate 11. Further, a field oxide film 16 is formed on the surface of the silicon substrate 11, and an electric conductor layer 17a is formed by a polycrystalline silicon on both the source area 14 and the field oxide film 16, while an electric conductor 17b is formed by a polycrystalline silicon on both the drain area 15 and the field oxide film 16. Between the gate electrode 13 and the conductor layer 17a there is formed a side-wall insulating film 12b, while between the gate electrode 13 and the conductor layer 17b there is formed a side-wall insulating film 12c. The gate electrode 13 and the conductor layers 17a, 17b are electrically insulated from each other by the side-wall insulating film s 12b and 12c. An interlayer insulating film 18 is formed on the conductor layers 17a, 17b and also on the gate electrode 13. And on the interlayer insulating film 18 there are formed wiring layers 19a and 19b by aluminum. The wiring layer 19a and the conductor layer 17a are electrically connected together by aluminum filled in a contact hole 20a formed in the interlayer insulating film 18, while the wiring layer 19b and the conductor layer 17b are electrically connected together by aluminum filled in a contact hole 20b formed in the interlayer insulating film 18.
How to produce the PSD transistor will be described below with reference to FIGS. 8A to 8H.
First, the field oxide film 16 for device separation is formed in a predetermined area on the surface of the silicon substrate 11 according to LOCOS (Local Oxidation of Silicon) method. Next, a first polycrystalline silicon film 17 is formed by deposition on the surface of the silicon substrate 11 according to a CVD (Chemical Vapor Deposition) method. Further, an impurity is ion-implanted in the first polycrystalline silicon film 17 (FIG. 8A).
A silicon oxide film 18 is formed by deposition on the first polycrystalline silicon film 17 according to the CVD method (FIG. 8B).
The portion of the first polycrystalline silicon film 17 and that of the silicon oxide film 18 corresponding to the gate electrode-forming portion of the PSD transistor are removed by reactive ion etching (FIG. 8C).
Thereafter the silicon substrate 11 is thermally oxidized (FIG. 8D). By the thermal diffusion of the silicon substrate 11, a gate oxide film 12a and side-wall the surface of the silicon substrate at the gate electrode forming portion and on the surfaces of the first polycrystalline silicon film 17 on both sides thereof. By this thermal diffusion, moreover, the impurity which has been implanted into the first polycrystalline silicon film 17 is defined into the silicon substrate 11, whereby there are formed source and drain areas 14, 15 (FIG. 8E).
A second polycrystalline silicon film 23 is formed by deposition on the silicon oxide film 18 and also on the gate oxide film 12a according to the CVD method (FIG. 8F).
The second polycrystalline silicon film 23 and the silicon oxide film 18 are removed selectively by etching to form a gate electrode 13 (FIG. 8G).
On the first polycrystalline silicon film 17 and the gate electrode 13 there is formed a silicon oxide film 18 by deposition according to the CVD method. The silicon oxide film 18 on the first polycrystalline silicon film 17 is partially removed by etching to form a contact hole 20. Then, an aluminum wiring layer 19 is formed on the silicon oxide film 18 by vacuum deposition. The aluminum wiring layer 19 and the first polycrystalline silicon film 17 are electrically connected together by aluminum filled in the contact hole 20 (FIG. 8H). The PSD transistor manufacturing process is completed by the above steps.
Features of the PSD transistor will be described below in comparison with the conventional MOS field effect transistor with reference to FIGS. 6 and 7.
(1) In the conventional MOS field effect transistor, the source and drain areas 4, 5 are formed by ion implantation directly into the silicon substrate 1 followed by thermal diffusion. Consequently, crystal defects 4a and 5a were generated in the source and drain regions 4 and 5 by the ion implantation.
Meanwhile, in the PSD transistor, ions for forming the source and drain regions 14 and 15 are implanted into the first polycrystalline silicon films 17a and 17b. The implanted ions remain in the first polycrystalline silicon films 17a and 17b. Thereafter, the implanted ions are thermally diffused to form the source and drain regions 14 and 15. Consequently, generation of crystal defects by the ion implantation is suppressed in the source and drain regions 14 and 15.
(2) In the conventional MOS field effect transistor, a contact hole 9a is formed above the source area 4 and it is filled with aluminum to thereby make electrical connection between the wiring layer 8a and the source area 4, while a contact hole 9b is formed above the drain area 5 and it is filled with aluminum to thereby make electrical connection between the wiring layer 8b and the drain area 5. Since the source and drain areas 4, 5 have been reduced in size with the demand for miniaturization of the MOS field effect transistor, it is becoming difficult to positively locate the contact holes 9a and 9b above the source and drain areas 4, 5 respectively, resulting in frequent occurrence of poor electrical connection between the source, drain areas 4, 5 and the wiring layer 8a, 8b.
On the other hand, in the PSD transistor, a contact hole 20a is formed above the first polycrystalline silicon film 17a extending from the surface of the source area 14 to the surface of the field oxide film 16 and it is filled with aluminum to thereby make electrical connection between the source area 14 and the wiring layer 19a, while a contact hole 20b is formed above the first polycrystalline silicon film 17b extending from the surface of the drain area 15 to the surface of the field oxide film 16 and it is filled with aluminum to thereby make electrical connection between the drain area 15 and the wiring layer 19b. Therefore, even if the source and drain areas 14, 15 are reduced in size, it is possible to positively effect electrical connection between the source, drain areas 14, 15 and the wiring layers 19a, 19b if only the area of the first polycrystalline silicon films 17a, 17b is sufficiently large.
(3) The miniaturization of the MOS field effect transistor can be attained also by making more shallow the source and drain areas.
In the conventional MOS field effect transistor, the source and drain areas 4, 5 are formed by direct ion implantation into the major surface of the semiconductor substrate 1 followed by thermal diffusion. On the other hand, in the PSD transistor, the source and drain areas 14, 15 are formed by ion implantation into the first polycrystalline silicon films 17a, 17b followed by thermal diffusion. In the PSD transistor, the source and drain regions can be made shallower than in the conventional MOS field effect transistors, since the starting point of diffusing ions is different. In addition, since no crystal defect is generated in the source and drain regions of the PSD transistor, it is not necessary to repair the crystal defects. Consequently, the time required for thermal diffusion can be made shorter, which leads to the formation of shallower source and drain regions.
(4) The demand for miniaturization of the MOS field effect transistor also leads to shortening of the channel length. In the conventional MOS field effect transistor, the channel length, indicated at 10, and the width of the gate electrode 3 are the same, so there has been the problem that the shorter the channel length 10, the smaller the sectional area of the gate electrode 3, resulting in increased electrical resistance of the gate electrode 3. On the other hand, in the PSD transistor, since the width of the upper portion of the gate electrode 13 is larger than the channel length indicated at 21, it is possible to enlarge the sectional area of the upper portion of the gate electrode 13 even when the channel length 21 is made small, whereby the gate resistance can be made low.
With these features, the PSD transistor can be attained its miniaturization, speed-up and low power consumption as compared with the conventional MOS field effect transistor.
However, the PSD transistor involves two drawbacks, which will be explained below.
In the conventional PSD transistor, as shown in FIG. 8E, the gate oxide film 12a and the side-wall insulating film 12b, 12c are formed at the same time by thermal oxidation. The thermal oxidation is performed so that the gate oxide film 12a has an optimum thickness. The side-wall insulating film s 12b and 12c formed by the said thermal oxidation may be destroyed by a certain difference between the voltage applied to the gate electrode 13 and that applied to the polycrystalline silicon film s 17a, 17b, resultant in electrical connection between the gate electrode 13 and the polycrystalline silicon films 17a, 17b.
Now, polycrystalline silicon doped with impurities is more susceptible to oxidation than polycrystalline silicon which is not doped. It has been experimentally known that n type impurities facilitates oxidation more than the p type impurities. Therefore, if the impurity to be implanted into the polycrystalline silicon films 17a and 17b is made n-type, the above-mentioned drawback can be remedied to some extent because the side-wall insulating films 12b and 12c become thicker than the gate oxide film 12a. A transistor where in the side-wall insulating films 12b and 12c are made thicker than the gate oxide film 12a by implantation of an n-type impurity into the polycrystalline silicon films 17a and 17b is disclosed in IEEE ELECTRON DEVICE LETTERS, VOL. EDL-7, NO. 5, May 1986, pp. 314-316 "A MOS Transistor with Self-Aligned Polysilicon Source-Drain".
However, the following problems are involved in the first drawback of the PSD transistor.
According to the conventional method wherein the side-wall insulating film 12b and 12c are made thicker than the gate oxide film 12a by the implantation of an n-type impurity into the polycrystalline silicon films 17a and 17b, the gate oxide film 12a and the side-wall insulating films 12a, 12c are formed at the same time by thermal oxidation. The thermal oxidation is performed so that the gate oxide film 12a has an optimum thickness. The gate oxide film 12a must be made thin in order to operate the MOS transistor with low power consumption. Since the gate oxide film 12a and the side-wall insulating films 12b and 12c are simultaneously formed in the prior art method, the side-wall insulating films 12b and 12c are inevitably made thinner when the gate oxide film 12a is made thinner. In this method, therefore, the reduction in thickness of the gate oxide film 12a causes the likelihood of dielectric breakdown of the side-wall insulating films 12b and 12c.
When p type impurities (for example, boron) are implanted into the polycrystalline silicon films 17a and 17b, the thickness of the gate oxide film 12a will be approximately the same as that of the side-wall insulating films 12b and 12c, in accordance with the conventional method of simultaneously forming the gate oxide film 12a and the side-wall insulating films 12b and 12c. In pMOS and complementary MOS transistors, therefore, it has heretofore been difficult to form the side-wall insulating films 12b and 12c to the extend of not causing dielectric breakdown.
The other drawback of the PSD transistor will be explained below.
The PSD transistor employs the polycrystalline silicon film s 17a and 17b respectively is an electric conductor layer for electrical connection between the source area 14 and the aluminum wiring layer 19a and an electric conductor layer for electrical connection between the drain area 15 and the aluminum wiring layer 19b. Since the polycrystalline silicon is high in resistance, it exerts a bad influence on the speed-up and reduction in power consumption of the PSD transistor.
However, the problem that the polycrystalline silicon is high in resistance can be overcome by forming a highly electroconductive metal silicide layer on the polycrystalline silicon film s 17a and 17b. FIG. 9 is a sectional view of a PSD transistor with a metal silicide layer formed on a polycrystalline silicon film. Numeral 39 indicates the metal silicide layer. In FIG. 9, numeral 31 denotes a silicon substrate, 32 a gate oxide film, 33 a polycrystalline silicon film, 34 a source area, 35 a drain area, 36 a field oxide film, 37 a polycrystalline silicon film and 38 a silicon oxide film.
The method of producing such PSD transistor is described, for example, in Japanese Patent Laying-Open No. 118651/1980.
A PSD transistor in which, although the gate oxide film and the side-wall insulating films are simultaneously formed, the side-wall insulating films are made thicker than the gate oxide film by implanting n type impurities in the polycrystalline silicon film, and in which a metal silicide layer is formed on the polycrystalline silicon film is disclosed in U.S. patent application Ser. No. 272,994 filed on Nov. 17, 1988 by the same applicant of the present invention on Apr. 1, 1988.